Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen. Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. IEEE Trans. on CAD of Integrated Circuits and Systems, 42(1):266-279, 2023. [doi]
@article{PatyalCLFC23,
title = {Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings},
author = {Abhishek Patyal and Hung-Ming Chen and Mark Po-Hung Lin and Guan-Qi Fang and Simon Yi-Hung Chen},
year = {2023},
doi = {10.1109/TCAD.2022.3174166},
url = {https://doi.org/10.1109/TCAD.2022.3174166},
researchr = {https://researchr.org/publication/PatyalCLFC23},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {42},
number = {1},
pages = {266-279},
}