VERILAT: verification using logic augmentation and transformations

Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan. VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems, 19(9):1041-1051, 2000. [doi]

Authors

Debjyoti Paul

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Mitrajit Chatterjee

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Dhiraj K. Pradhan

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