Debjyoti Paul, Mitrajit Chatterjee, Dhiraj K. Pradhan. VERILAT: verification using logic augmentation and transformations. IEEE Trans. on CAD of Integrated Circuits and Systems, 19(9):1041-1051, 2000. [doi]
@article{PaulCP00,
title = {VERILAT: verification using logic augmentation and transformations},
author = {Debjyoti Paul and Mitrajit Chatterjee and Dhiraj K. Pradhan},
year = {2000},
doi = {10.1109/43.863644},
url = {http://doi.ieeecomputersociety.org/10.1109/43.863644},
tags = {logic, transformation},
researchr = {https://researchr.org/publication/PaulCP00},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {19},
number = {9},
pages = {1041-1051},
}