BCH code based multiple bit error correction in finite field multiplier circuits

Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan, Saraju P. Mohanty. BCH code based multiple bit error correction in finite field multiplier circuits. In Proceedings of the 12th International Symposium on Quality Electronic Design, ISQED 2011, Santa Clara, California, USA, 14-16 March 2011. pages 615-620, IEEE, 2011. [doi]

Authors

Mahesh Poolakkaparambil

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Jimson Mathew

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Abusaleh M. Jabir

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Dhiraj K. Pradhan

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Saraju P. Mohanty

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