The following publications are possibly variants of this publication:
- A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOSPeng Chen 0022, Xi Meng, Jun Yin 0001, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski. tcasI, 69(1):51-63, 2022. [doi]
- An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference SpursFeng-Wei Kuo, Masoud Babaie, Huan-Neng Ron Chen, Lan-chou Cho, Chewnpu Jou, Mark Chen 0001, Robert Bogdan Staszewski. tcas, 65-I(11):3756-3768, 2018. [doi]
- Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOSPeng Chen 0022, Jun Yin 0001, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski. tcasI, 69(1):196-206, 2022. [doi]