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Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage

Junius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah. Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain Usage. In 35th International Conference on Field-Programmable Logic and Applications, FPL 2025, Leiden, The Netherlands, September 1-5, 2025. pages 27-36, IEEE, 2025. [doi]

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Junius Pun

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Xilai Dai

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Grace Zgheib

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Mahesh A. Iyer

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Andrew Boutros

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Vaughn Betz

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Mohamed S. Abdelfattah

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