Table of Contents

• Energy-Efficient DNNs on FPGAs for Edge-Cloud Computer VisionQaisar Farooq, Idilio Drago. 1-2 [doi]
• GEF: A GNN-Based Evaluation Framework for FPGA Routing ArchitectureYuanqi Wang, Yunfei Dai, Jiangnan Li, Kaixiang Zhu, Huizhen Kuang, Hao Zhou, Eric Ren, Xifan Tang, Weijun Qin, Tao Li, Lingli Wang. 1-9 [doi]
• ATAPP: Architecture and Technology Aware Power Predictor for Unseen FPGASZhigang Wei, Aman Arora 0001, Emily Shriver, Lizy K. John. 1-10 [doi]
• Live Demonstration: Continuous Processing of Event-Data with Graph Convolutional Neural Networks Implemented for SoC FPGAPiotr Wzorek, Kamil Jeziorek, Marcin Kowalczyk, Krzysztof Blachut, Tomasz Kryjak, Marek Gorgon. 1 [doi]
• FPGAs with FABulous - Framework and ChipsDirk Koch, Myrtle Shah, King Lok Chung, Jonas Kuenstler, Marcel Jung, Jakob Ternes, Asma Mohsin, Gennadiy Knis. 1 [doi]
• Versatile Place and Route with Continuous Routing Runtime Prediction and Smart Route TerminationAndrew David Gunter, Steven J. E. Wilton. 1 [doi]
• Using Data to Reduce Uncertainty in FPGA RoutingAndrew David Gunter, Steven J. E. Wilton. 1-2 [doi]
• Interconnection-Aware Resynthesis for Improving FPGA Physical DesignXiaoke Wang, Dirk Stroobandt. 1-2 [doi]
• Virtualization and Dynamic Reconfiguration of Custom Instruction Accelerators (CIA) in RISC-V Embedded SystemsBea Healy, Brandon Freiberger, Jonas Kuenstler, King Lok Chung, Emil Cozac, Meinhard Kissich, Gennadiy Knis, Ron Sass, Dirk Koch, Jan Gray, Guy Lemieux. 1-9 [doi]
• Compile in Seconds and Run on an FPGA with DynaRapidAndrea Guerrieri, Isaac John Wetenkamp, Chris Lavin, Eddie Hung, Lana Josipovic, Paolo Ienne. 1 [doi]
• FPGA-Based MPSoCs for High-Performance Sensor Fusion: Accelerating Covariance IntersectionHazem M. Sharf, Mohamed Hassan. 1-10 [doi]
• Multi-FPGA Programming Using OpenMPPedro Henrique Di Francia Rosso, Guido Araujo. 1 [doi]
• Towards Accelerated Healthcare Federated System Through Heterogeneous AcceleratorsGiuseppe Sorrentino, Davide Conficconi. 1-2 [doi]
• Open-Source FPGA Routing Runtime Prediction for Improved Productivity Via Smart Route TerminationAndrew David Gunter, Steven J. E. Wilton. 1-9 [doi]
• Programmable Congestion Generator for Evaluating FPGA Interconnect RobustnessAtreyee Saha, Sandesh Goyal, Aashish Tripathi. 1-9 [doi]
• NPX: Automating Neuromorphic Processor Design from Spike-Based Learning to FPGA PrototypingKyuseung Han, Hyeonguk Jang, Sukho Lee, Sung-Eun Kim, Kyudong Hwang, Jae-Jin Lee. 1 [doi]
• Reducing FPGA Placement Runtime by Clustering of Netlist BlocksMarkus Rein, Dirk Stroobandt. 1-2 [doi]
• Routino: Accelerating FPGA Routing Through Efficient Memory RepresentationDavide Nicolini, Corrado De Sio, Eleonora Vacca, Luca Sterpone. 1-9 [doi]
• ReconFormer: A Multi-Level Run-Time Reconfigurable System-on-Chip for Accelerating TransformersJe Yang, Gabriele Tombesi, Joseph Zuckerman, Luca P. Carloni. 10-17 [doi]
• FLAIC: A Novel FPGA Logic Architecture via Fine-Grained Cut Topology AnalysisXianfeng Cao, Huizhen Kuang, Yuanqi Wang, Lingli Wang. 18-26 [doi]
• Double Duty: FPGA Architecture to Enable Concurrent LUT and Adder Chain UsageJunius Pun, Xilai Dai, Grace Zgheib, Mahesh A. Iyer, Andrew Boutros, Vaughn Betz, Mohamed S. Abdelfattah. 27-36 [doi]
• DEFA: Design Space Exploration for FPGA Overlay Accelerators Through Frequency Prediction and Bayesian OptimizationQilong Zhu, Yunfei Dai, Shiyan Bi, Huizhen Kuang, Dylan Wang, Wenbo Yin, Lingli Wang. 37-45 [doi]
• FINN-GL: Generalized Mixed-Precision Extensions for FPGA-Accelerated LSTMSShashwat Khandelwal, Jakoba Petri-Koenig, Thomas B. Preußer, Michaela Blott, Shanker Shreejith. 46-54 [doi]
• Multiplexer Optimizations for Virtex FPGAsNicolai Fiege, Martin Hardieck, Peter Zipf. 55-59 [doi]
• Identifying Sat Resilient Blocks Through LUT Switching Analysis for Breaking Compound Logic Locking SchemesBinbin Wang, Xinmu Wang, Xinyu Zhang, Shibo Tang, Huisi Zhou, Wei Hu. 60-67 [doi]
• URAM-Based Asynchronous FIFO Design for Improved Throughput and FPGA RAM UsageMartim Rosado, Pedro Tomás, Nuno Roma, André David. 68-72 [doi]
• From Errors to Solutions: LLM-Powered Command Scripting for FPGA Cad ToolsMohamed A. Elgammal, Vaughn Betz. 73-82 [doi]
• TRPlaceFPGA-MP: A Two-Stage Reinforcement Learning Framework for Fast FPGA Macro PlacerQin Luo, Xinshi Zang, Evangeline F. Y. Young, Martin D. F. Wong. 83-90 [doi]
• FAME: FPGA Acceleration of Secure Matrix Multiplication with Homomorphic EncryptionZhihan Xu, Rajgopal Kannan, Viktor K. Prasanna. 100-109 [doi]
• 2Opt: Novel Fine-Tuning and Folding Algorithms for FPGA-Based DNN AcceleratorsMuhammad Shakeel Akram, Bogaraju Sharatchandra Varma, Vincent Meyers, Mehdi B. Tahoori, Dewar Finlay. 110-119 [doi]
• AffiNiTy: A Multi-Scalar Multiplication Accelerator with a Novel Batched Inversion ArchitectureTong Wu 0007, Niall Emmart, Oliver Diessel. 130-138 [doi]
• EViL: An Efficient Vision-LSTM Accelerator Based on FPGAZexuan Deng, Han Jiao 0003, Wenjin Huang, Yihua Huang 0005. 139-143 [doi]
• SparseDPD: A Sparse Neural Network-Based Digital Predistortion FPGA Accelerator for RF Power Amplifier LinearizationManno Versluis, Yizhuo Wu, Chang Gao. 154-158 [doi]
• Routing Struggle: A Metric to Quantify RoutabilitySadegh Yazdanshenas, Jeffrey Chromczak. 186-194 [doi]
• Aspo: Constraint-Aware Bayesian Optimization for Fpga-Based Soft ProcessorsHaoran Wu, Ce Guo, Wayne Luk, Robert Mullins 0001. 195-203 [doi]
• Improving Boolean Satisfiability-Based Modulo SchedulingNicolai Fiege, Peter Zipf. 204-212 [doi]
• Maximum FPGA: A 32K-Point 32-Parallel Floating Point FFTMartin Langhammer, Bogdan Pasca 0001. 213-221 [doi]
• Cocotb-Pynq: Co-Simulating Python+RTL Applications Targeting Pynq Platforms with CocotbGavin Lusby, Nachiket Kapre. 222-226 [doi]
• EQViTA: an End-To-End Quantized Vision Transformer Accelerator Implemented on Resource-Constrained FPGAsJiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang 0036, Jinmei Lai 0001. 227-235 [doi]
• FPGA Stereo Visual Slam with Efficient Stereo Feature Matching and Key-Frame GenerationMiyuru Thathsara, Damith Anhettigama, Siew Kei Lam. 236-244 [doi]
• A High-Performance and Resource-Efficient FPGA-Based Multi-Object Tracking System Using Event CamerasWei Xiong, Jianfan Zhang, Xingzhe Zhu, Jiacheng Cao, Jian Wang, Jinmei Lai. 245-253 [doi]
• Four-Input Lookup Table (LUT4) and Architectural Enhancements Enable Power Efficient Mid-Range FPGAsSatwant Singh, Michael Schneider, Ziad Aboud, Jonathan Peterson, Senani Gunaratna, Ting Yew, Cindy Lee, Rick Crotty. 254-262 [doi]
• Refining Datapath for Microscaling ViTsCan Xiao, Jianyi Cheng, Yiren Zhao. 263-272 [doi]
• Towards Instruction-Controlled In-Pipeline GEMM Acceleration in a Dual-Issue RISC-V Core for Edge ApplicationsAhmad Othman, Darmen Ilyas, Ahmed Kamaleldin, Diana Göhringer. 273-281 [doi]
• Design Space Exploration of Fast RISC-V Processors for Scalable Kilo-Core FPGA SystemsRiadh Ben Abdelhamid, Vladislav Válek, Kevin Klein, Dirk Koch. 282-290 [doi]
• DMA Calypte: Open-Source Ultra-Low Latency DMA Engine for FPGAsVladislav Válek, Martin Spinler, Jakub Cabal, Tomás Martínek. 291-295 [doi]
• Hybrid Weightless Neural Networks for Efficient Edge InferenceMugdha P. Jadhao, Alan T. L. Bacellar, Shashank Nag, Igor D. S. Miranda, Felipe M. G. França, Lizy K. John. 296-304 [doi]
• Accelerating Transposed Convolutions on FPGA-Based Edge DevicesJude Haris, José Cano 0001. 305-313 [doi]
• AMD Versal Implementations of FAM and SSCA EstimatorsCarol Jingyi Li, Ruilin Wu, Philip H. W. Leong. 314-322 [doi]
• GAMA: High-Performance GEMM Acceleration on AMD Versal ML-Optimized AI EnginesKaustubh Manohar Mhatre, Endri Taka, Aman Arora 0001. 323-331 [doi]
• NeuGEMM: A Reordering-Free Unified GEMM-Conv2D Accelerator for Lightweight Neuromorphic ProcessorsHyeonguk Jang, Sukho Lee, Jae-Jin Lee, Kyuseung Han. 332-336 [doi]
• Accelerating K-Means: A Vectorized Approach for AI Engines & Neural Processing UnitsEleonora Cabai, Giuseppe Sorrentino, Marco Domenico Santambrogio, Davide Conficconi. 337-341 [doi]
• Maximizing Resource Utilization for Stencil ComputingPedro Henrique Di Francia Rosso, Guido Araujo. 348-349 [doi]
• Performance Impact on Reducing Energy Consumption Applying Adaptive Stream-Based Entropy Coding on FPGATaku Nishikawa, Koichi Marumo, Shinichi Yamagiwa. 355 [doi]
• Analytical Buffer Sizing for Neural Network Inference Applications on FPGAsLukas Stasytis, Felix Jentzsch, Zsolt István. 356 [doi]
• Connection Tracking at 400 GbpsDavid Vodák, Oliver Gurka, Jirí Matousek 0002, Daniel Kondys. 361 [doi]