The following publications are possibly variants of this publication:
- An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock GeneratorsXueyi Yu, Yuanfeng Sun, Woogeun Rhee, Zhihua Wang. jssc, 44(9):2426-2436, 2009. [doi]
- A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise FilteringXueyi Yu, Yuanfeng Sun, Li Zhang, Woogeun Rhee, Zhihua Wang. isscc 2008: 346-347 [doi]
- A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency DividerBaoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang. iscas 2007: 3051-3054 [doi]