Matthias Raffelsieper, Mohammad Reza Mousavi, Chris W. H. Strolenberg. Checking and deriving module paths in Verilog cell library descriptions. In Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010. pages 1506-1511, IEEE, 2010. [doi]
@inproceedings{RaffelsieperMS10,
title = {Checking and deriving module paths in Verilog cell library descriptions},
author = {Matthias Raffelsieper and Mohammad Reza Mousavi and Chris W. H. Strolenberg},
year = {2010},
url = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5457050},
researchr = {https://researchr.org/publication/RaffelsieperMS10},
cites = {0},
citedby = {0},
pages = {1506-1511},
booktitle = {Design, Automation and Test in Europe, DATE 2010, Dresden, Germany, March 8-12, 2010},
publisher = {IEEE},
}