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Anand Raghunathan, Sujit Dey, Niraj K. Jha. Glitch Analysis and Reduction in Register Transfer Level. In DAC. pages 331-336, 1996. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Register transfer level power optimization with emphasis on glitch analysis and reductionAnand Raghunathan, Sujit Dey, Niraj K. Jha. tcad, 18(8):1114-1131, 1999. [doi] TAO: regular expression-based register-transfer level testability analysis and optimizationSrivaths Ravi, Ganesh Lakshminarayana, Niraj K. Jha. tvlsi, 9(6):824-832, 2001. [doi]
The following publications are possibly variants of this publication: