Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan. VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. In Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay, editors, Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Volume 7373 of Lecture Notes in Computer Science, pages 258-269, Springer, 2012. [doi]
@inproceedings{RahamanMJP12, title = {VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases}, author = {Hafizur Rahaman and Jimson Mathew and Abusaleh M. Jabir and Dhiraj K. Pradhan}, year = {2012}, doi = {10.1007/978-3-642-31494-0_30}, url = {http://dx.doi.org/10.1007/978-3-642-31494-0_30}, researchr = {https://researchr.org/publication/RahamanMJP12}, cites = {0}, citedby = {0}, pages = {258-269}, booktitle = {Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings}, editor = {Hafizur Rahaman and Sanatan Chattopadhyay and Santanu Chattopadhyay}, volume = {7373}, series = {Lecture Notes in Computer Science}, publisher = {Springer}, isbn = {978-3-642-31493-3}, }