Ritesh Rajore, Ganesh Garga, H. S. Jamadagni, S. K. Nandy. Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture. In 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008 Leuven, Belgium. pages 49-54, IEEE Computer Society, 2008. [doi]
@inproceedings{RajoreGJN08,
title = {Reconfigurable Viterbi decoder on mesh connected multiprocessor architecture},
author = {Ritesh Rajore and Ganesh Garga and H. S. Jamadagni and S. K. Nandy},
year = {2008},
doi = {10.1109/ASAP.2008.4580153},
url = {http://dx.doi.org/10.1109/ASAP.2008.4580153},
tags = {architecture},
researchr = {https://researchr.org/publication/RajoreGJN08},
cites = {0},
citedby = {0},
pages = {49-54},
booktitle = {19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008 Leuven, Belgium},
publisher = {IEEE Computer Society},
}