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90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation

Anisha Ramesh, Si-Young Park, Paul R. Berger. 90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation. IEEE Trans. on Circuits and Systems, 58-I(10):2432-2445, 2011. [doi]

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Anisha Ramesh

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Si-Young Park

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Paul R. Berger

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