Anisha Ramesh, Si-Young Park, Paul R. Berger. 90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation. IEEE Trans. on Circuits and Systems, 58-I(10):2432-2445, 2011. [doi]
@article{RameshPB11,
title = {90 nm 32 times 32 bit Tunneling SRAM Memory Array With 0.5 ns Write Access Time, 1 ns Read Access Time and 0.5 V Operation},
author = {Anisha Ramesh and Si-Young Park and Paul R. Berger},
year = {2011},
doi = {10.1109/TCSI.2011.2123630},
url = {http://dx.doi.org/10.1109/TCSI.2011.2123630},
researchr = {https://researchr.org/publication/RameshPB11},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on Circuits and Systems},
volume = {58-I},
number = {10},
pages = {2432-2445},
}