FPGA-based high performance page layout segmentation

Nalini K. Ratha, Anil K. Jain, Diane T. Rover. FPGA-based high performance page layout segmentation. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 29-34, IEEE Computer Society, 1996. [doi]

Authors

Nalini K. Ratha

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Anil K. Jain

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Diane T. Rover

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