Fast test generation for circuits with RTL and gate-level views

Srivaths Ravi, Niraj K. Jha. Fast test generation for circuits with RTL and gate-level views. In Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001. pages 1068-1077, IEEE Computer Society, 2001.

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.