FPGA power reduction by guarded evaluation considering physical information - researchr publication authors

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Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson. FPGA power reduction by guarded evaluation considering physical information. In Srinivas Katkoori, Matthew R. Guthaus, Ayse Kivilcim Coskun, Andreas Burg, Ricardo Reis, editors, 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012. pages 271-274, IEEE, 2012. [doi]

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