An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)

B. Naresh Kumar Reddy, Sireesha. An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC). In S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh, editors, VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers. Volume 892 of Communications in Computer and Information Science, pages 631-640, Springer, 2018. [doi]

Authors

B. Naresh Kumar Reddy

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Sireesha

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