B. Naresh Kumar Reddy, Sireesha. An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC). In S. Rajaram, N. B. Balamurugan, D. Gracia Nirmala Rani, Virendra Singh, editors, VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers. Volume 892 of Communications in Computer and Information Science, pages 631-640, Springer, 2018. [doi]
@inproceedings{ReddyS18-4,
title = {An Energy-Efficient Core Mapping Algorithm on Network on Chip (NoC)},
author = {B. Naresh Kumar Reddy and Sireesha},
year = {2018},
doi = {10.1007/978-981-13-5950-7_52},
url = {https://doi.org/10.1007/978-981-13-5950-7_52},
researchr = {https://researchr.org/publication/ReddyS18-4},
cites = {0},
citedby = {0},
pages = {631-640},
booktitle = {VLSI Design and Test - 22nd International Symposium, VDAT 2018, Madurai, India, June 28-30, 2018, Revised Selected Papers},
editor = {S. Rajaram and N. B. Balamurugan and D. Gracia Nirmala Rani and Virendra Singh},
volume = {892},
series = {Communications in Computer and Information Science},
publisher = {Springer},
isbn = {978-981-13-5950-7},
}