A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery

William Redman-White, Martin Bugbee, Steve Dobbs, X. Wu, Richard A. H. Balmford, Jonah Nuttgens, Umer Salim Kiani, Richard Clegg, Gerrit W. den Besten. A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery. In William Redman-White, Anthony J. Walton, editors, ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008. pages 170-173, IEEE, 2008. [doi]

@inproceedings{Redman-WhiteBDW08,
  title = {A robust 1.5Gb/s + 3Gb/s serial PHY with feed-forward correction clock and data recovery},
  author = {William Redman-White and Martin Bugbee and Steve Dobbs and X. Wu and Richard A. H. Balmford and Jonah Nuttgens and Umer Salim Kiani and Richard Clegg and Gerrit W. den Besten},
  year = {2008},
  doi = {10.1109/ESSCIRC.2008.4681819},
  url = {https://doi.org/10.1109/ESSCIRC.2008.4681819},
  researchr = {https://researchr.org/publication/Redman-WhiteBDW08},
  cites = {0},
  citedby = {0},
  pages = {170-173},
  booktitle = {ESSCIRC 2008 - 34th European Solid-State Circuits Conference, Edinburgh, Scotland, UK, 15-19 September 2008},
  editor = {William Redman-White and Anthony J. Walton},
  publisher = {IEEE},
  isbn = {978-1-4244-2361-3},
}