A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability

Dirk Reese, Eric Chun, Sammy Cheung, Edmond Lau, Michael Chu, Gwen Liang, Nghia Van Tran, Brad Vest, Richard Smolen, Minchang Liang, Seshan Sekariapuram, Behzad Nouban, Myron Wong, John Costello, John Turner. A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability. In Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998. pages 265-268, IEEE, 1998. [doi]

@inproceedings{ReeseCCLCLTVSLSNWCT98,
  title = {A 6.9 ns, 560 macrocell, in system programmable, CMOS PLD with 3.3-5 volt I/O capability},
  author = {Dirk Reese and Eric Chun and Sammy Cheung and Edmond Lau and Michael Chu and Gwen Liang and Nghia Van Tran and Brad Vest and Richard Smolen and Minchang Liang and Seshan Sekariapuram and Behzad Nouban and Myron Wong and John Costello and John Turner},
  year = {1998},
  doi = {10.1109/CICC.1998.694977},
  url = {https://doi.org/10.1109/CICC.1998.694977},
  researchr = {https://researchr.org/publication/ReeseCCLCLTVSLSNWCT98},
  cites = {0},
  citedby = {0},
  pages = {265-268},
  booktitle = {Proceedings of the IEEE 1998 Custom Integrated Circuits Conference, CICC 1998, Santa Clara, CA, USA, May 11-14, 1998},
  publisher = {IEEE},
  isbn = {0-7803-4292-5},
}