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A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor. A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocessors and Microsystems, 28(5-6):291-301, 2004. [doi]

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Javier Resano

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Diederik Verkest

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Daniel Mozos

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Serge Vernalde

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Francky Catthoor

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