Javier Resano, Diederik Verkest, Daniel Mozos, Serge Vernalde, Francky Catthoor. A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs. Microprocessors and Microsystems, 28(5-6):291-301, 2004. [doi]
@article{ResanoVMVC04,
title = {A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs},
author = {Javier Resano and Diederik Verkest and Daniel Mozos and Serge Vernalde and Francky Catthoor},
year = {2004},
doi = {10.1016/j.micpro.2004.03.015},
url = {http://dx.doi.org/10.1016/j.micpro.2004.03.015},
tags = {data-flow, design},
researchr = {https://researchr.org/publication/ResanoVMVC04},
cites = {0},
citedby = {0},
journal = {Microprocessors and Microsystems},
volume = {28},
number = {5-6},
pages = {291-301},
}