The following publications are possibly variants of this publication:
- Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAsMustafa Demirci, Pedro Reviriego, Juan Antonio Maestro. mr, 56:221-227, 2016. [doi]
- Unequal Error Protection Codes Derived from Double Error Correction Orthogonal Latin Square CodesMustafa Demirci, Pedro Reviriego, Juan Antonio Maestro. TC, 65(9):2932-2938, 2016. [doi]
- Single error correction, double error detection and double adjacent error correction with no mis-correction codeHo-yoon Jun, Yong-Surk Lee. ieiceee, 10(20):20130743, 2013. [doi]
- Low delay non-binary error correction codes based on Orthogonal Latin SquaresFrancisco Garcia-Herrero, Alfonso Sánchez-Macián, Juan Antonio Maestro. integration, 76:55-60, 2021. [doi]
- Adaptive error correction in Orthogonal Latin Square Codes for low-power, resilient on-chip interconnection networkSeung Eun Lee. mr, 53(3):509-511, 2013. [doi]
- Fault tolerant encoders for Single Error Correction and Double Adjacent Error Correction codesShanshan Liu, Pedro Reviriego, Juan Antonio Maestro, Liyi Xiao. mr, 81:167-173, 2018. [doi]