Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan. The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage. IEEE Trans. VLSI Syst., 20(5):911-924, 2012. [doi]
@article{RitheCGWDGBC12,
title = {The Effect of Random Dopant Fluctuations on Logic Timing at Low Voltage},
author = {Rahul Rithe and Sharon Chou and Jie Gu and Alice Wang and Satyendra Datla and Gordon Gammie and Dennis Buss and Anantha Chandrakasan},
year = {2012},
doi = {10.1109/TVLSI.2011.2124477},
url = {http://dx.doi.org/10.1109/TVLSI.2011.2124477},
researchr = {https://researchr.org/publication/RitheCGWDGBC12},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {20},
number = {5},
pages = {911-924},
}