Philippe Royannez, Amara Amara. A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. In 6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA. pages 24-28, IEEE Computer Society, 1996. [doi]
@inproceedings{RoyannezA96,
title = {A 1.0ns 64-bits GaAs Adder using Quad tree algorithm},
author = {Philippe Royannez and Amara Amara},
year = {1996},
url = {http://csdl.computer.org/comp/proceedings/glsvlsi/1996/7502/00/75020024abs.htm},
researchr = {https://researchr.org/publication/RoyannezA96},
cites = {0},
citedby = {0},
pages = {24-28},
booktitle = {6th Great Lakes Symposium on VLSI (GLS-VLSI 96), March 22-23, 1996, Ames, IA, USA},
publisher = {IEEE Computer Society},
}