Shanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Kun-Lin Tsai. A bipartition-codec architecture to reduce power in pipelinedcircuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 20(2):343-348, 2001. [doi]
@article{RuanSLT01,
title = {A bipartition-codec architecture to reduce power in pipelinedcircuits},
author = {Shanq-Jang Ruan and Rung-Ji Shang and Feipei Lai and Kun-Lin Tsai},
year = {2001},
doi = {10.1109/43.908477},
url = {http://doi.ieeecomputersociety.org/10.1109/43.908477},
tags = {architecture},
researchr = {https://researchr.org/publication/RuanSLT01},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {20},
number = {2},
pages = {343-348},
}