The following publications are possibly variants of this publication:
- A bipartition-codec architecture to reduce power in pipelined circuitsShanq-Jang Ruan, Rung-Ji Shang, Feipei Lai, Shyh-Jong Chen, Xian-Jun Huang. iccad 1999: 84-90 [doi]
- ENPCO: an entropy-based partition-codec algorithm to reduce power for bipartition-codec architecture in pipelined circuitsShanq-Jang Ruan, Edwin Naroska, Yen-Jen Chang, Feipei Lai, Uwe Schwiegelshohn. tvlsi, 10(6):942-949, 2002. [doi]
- An entropy-based algorithm to reduce area overhead for bipartition-codec architecturePo-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai. iscas 2001: 49-52 [doi]
- Bipartition Architecture for Low Power JPEG Huffman DecoderShanq-Jang Ruan, Wei-te Lin. APCSAC 2007: 235-243 [doi]