Sequential circuit testability enhancement using a nonscan approach

Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel. Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst., 3(2):333-338, 1995. [doi]

Authors

Elizabeth M. Rudnick

This author has not been identified. Look up 'Elizabeth M. Rudnick' in Google

Vivek Chickermane

This author has not been identified. Look up 'Vivek Chickermane' in Google

Prithviraj Banerjee

This author has not been identified. Look up 'Prithviraj Banerjee' in Google

Janak H. Patel

This author has not been identified. Look up 'Janak H. Patel' in Google