Elizabeth M. Rudnick, Vivek Chickermane, Prithviraj Banerjee, Janak H. Patel. Sequential circuit testability enhancement using a nonscan approach. IEEE Trans. VLSI Syst., 3(2):333-338, 1995. [doi]
@article{RudnickCBP95,
title = {Sequential circuit testability enhancement using a nonscan approach},
author = {Elizabeth M. Rudnick and Vivek Chickermane and Prithviraj Banerjee and Janak H. Patel},
year = {1995},
doi = {10.1109/92.386233},
url = {http://doi.ieeecomputersociety.org/10.1109/92.386233},
tags = {testing, systematic-approach},
researchr = {https://researchr.org/publication/RudnickCBP95},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {3},
number = {2},
pages = {333-338},
}