Stefan Rusu, Jason Stinson, Simon Tam 0001, Justin Leung, Harry Muljono, Brian S. Cherkauer. A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. J. Solid-State Circuits, 38(11):1887-1895, 2003. [doi]
@article{RusuSTLMC03,
title = {A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache},
author = {Stefan Rusu and Jason Stinson and Simon Tam 0001 and Justin Leung and Harry Muljono and Brian S. Cherkauer},
year = {2003},
doi = {10.1109/JSSC.2003.818293},
url = {https://doi.org/10.1109/JSSC.2003.818293},
researchr = {https://researchr.org/publication/RusuSTLMC03},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {38},
number = {11},
pages = {1887-1895},
}