A design of 4-operand redundant binary parallel adder using neuron MOS

Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka. A design of 4-operand redundant binary parallel adder using neuron MOS. In ISCAS (4). pages 793-796, 2004.

Authors

Masahiro Sakamoto

This author has not been identified. Look up 'Masahiro Sakamoto' in Google

Shuusaku Mizukami

This author has not been identified. Look up 'Shuusaku Mizukami' in Google

Daisuke Hamano

This author has not been identified. Look up 'Daisuke Hamano' in Google

Hisato Fujisaka

This author has not been identified. Look up 'Hisato Fujisaka' in Google