A design of 4-operand redundant binary parallel adder using neuron MOS

Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka. A design of 4-operand redundant binary parallel adder using neuron MOS. In ISCAS (4). pages 793-796, 2004.

@inproceedings{SakamotoMHF04,
  title = {A design of 4-operand redundant binary parallel adder using neuron MOS},
  author = {Masahiro Sakamoto and Shuusaku Mizukami and Daisuke Hamano and Hisato Fujisaka},
  year = {2004},
  tags = {design},
  researchr = {https://researchr.org/publication/SakamotoMHF04},
  cites = {0},
  citedby = {0},
  pages = {793-796},
  booktitle = {ISCAS (4)},
}