A design of 4-operand redundant binary parallel adder using neuron MOS

Masahiro Sakamoto, Shuusaku Mizukami, Daisuke Hamano, Hisato Fujisaka. A design of 4-operand redundant binary parallel adder using neuron MOS. In ISCAS (4). pages 793-796, 2004.

Abstract

Abstract is missing.