High-speed architectures for Reed-Solomon decoders

Dilip V. Sarwate, Naresh R. Shanbhag. High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst., 9(5):641-655, 2001. [doi]

Authors

Dilip V. Sarwate

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Naresh R. Shanbhag

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