Dilip V. Sarwate, Naresh R. Shanbhag. High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst., 9(5):641-655, 2001. [doi]
@article{SarwateS01,
title = {High-speed architectures for Reed-Solomon decoders},
author = {Dilip V. Sarwate and Naresh R. Shanbhag},
year = {2001},
doi = {10.1109/92.953498},
url = {http://doi.ieeecomputersociety.org/10.1109/92.953498},
tags = {architecture},
researchr = {https://researchr.org/publication/SarwateS01},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {9},
number = {5},
pages = {641-655},
}