The following publications are possibly variants of this publication:
- Protecting Ownership of Reusable IP Core Generated during High Level SynthesisDeepak Kachave, Anirban Sengupta. ifip5-5 2016: 80-82 [doi]
- Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level SynthesisAnirban Sengupta, Saumya Bhadauria. access, 4:2198-2215, 2016. [doi]
- Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesisDipanjan Roy, Anirban Sengupta. fgcs, 71:89-101, 2017. [doi]
- Embedding low cost optimal watermark during high level synthesis for reusable IP core protectionAnirban Sengupta, Saumya Bhadauria, Saraju P. Mohanty. iscas 2016: 974-977 [doi]
- Triple-Phase Watermarking for Reusable IP Core Protection During Architecture SynthesisAnirban Sengupta, Dipanjan Roy, Saraju P. Mohanty. tcad, 37(4):742-755, 2018. [doi]
- Exploration of optimal functional Trojan-resistant hardware intellectual property (IP) core designs during high level synthesisAnirban Sengupta, Aditya Anshul, Rahul Chaurasia. mam, 103:104973, 2023. [doi]