Jae-sun Seo, Bernard Brezzo, Yong Liu, Benjamin D. Parker, Steven K. Esser, Robert K. Montoye, Bipin Rajendran, José A. Tierno, Leland Chang, Dharmendra S. Modha, Daniel J. Friedman. A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons. In Rakesh Patel, Tom Andre, Aurangzeb Khan, editors, 2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011. pages 1-4, IEEE, 2011. [doi]
@inproceedings{SeoBLPEMRTCMF11,
title = {A 45nm CMOS neuromorphic chip with a scalable architecture for learning in networks of spiking neurons},
author = {Jae-sun Seo and Bernard Brezzo and Yong Liu and Benjamin D. Parker and Steven K. Esser and Robert K. Montoye and Bipin Rajendran and José A. Tierno and Leland Chang and Dharmendra S. Modha and Daniel J. Friedman},
year = {2011},
doi = {10.1109/CICC.2011.6055293},
url = {http://dx.doi.org/10.1109/CICC.2011.6055293},
researchr = {https://researchr.org/publication/SeoBLPEMRTCMF11},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {2011 IEEE Custom Integrated Circuits Conference, CICC 2011, San Jose, CA, USA, Sept. 19-21, 2011},
editor = {Rakesh Patel and Tom Andre and Aurangzeb Khan},
publisher = {IEEE},
isbn = {978-1-4577-0222-8},
}