Circuit design of a dual-versioning L1 data cache

Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero. Circuit design of a dual-versioning L1 data cache. Integration, 45(3):237-245, 2012. [doi]

@article{SeyediACUHV12,
  title = {Circuit design of a dual-versioning L1 data cache},
  author = {Azam Seyedi and Adrià Armejach and Adrián Cristal and Osman S. Unsal and Ibrahim Hur and Mateo Valero},
  year = {2012},
  doi = {10.1016/j.vlsi.2011.11.015},
  url = {http://dx.doi.org/10.1016/j.vlsi.2011.11.015},
  researchr = {https://researchr.org/publication/SeyediACUHV12},
  cites = {0},
  citedby = {0},
  journal = {Integration},
  volume = {45},
  number = {3},
  pages = {237-245},
}