Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations - researchr publication authors

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K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz. Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. In Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa, editors, Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings. Volume 2778 of Lecture Notes in Computer Science, pages 313-323, Springer, 2003. [doi]

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