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Shan Shen, Tianxiang Shao, Xiaojing Shang, Yichen Guo, Ming Ling, Jun Yang 0006, Longxing Shi. TS Cache: A Fast Cache With Timing-Speculation Mechanism Under Low Supply Voltages. IEEE Trans. VLSI Syst., 28(1):252-262, 2020. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: RRS cache: a low voltage cache based on timing speculation SRAM with a reuse-aware cacheline remapping mechanismXiaojing Shang, Ming Ling, Shan Shen, Tianxiang Shao, Jun Yang. memsys 2019: 451-458 [doi]
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