On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time - researchr publication authors

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Jaidev Shenoy, Kelly A. Ockunzzi, Virendra Singh, Kushal Kamal. On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. In 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019. pages 106-111, IEEE, 2019. [doi]

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