On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time

Jaidev Shenoy, Kelly A. Ockunzzi, Virendra Singh, Kushal Kamal. On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time. In 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019. pages 106-111, IEEE, 2019. [doi]

@inproceedings{ShenoyOSK19,
  title = {On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test Time},
  author = {Jaidev Shenoy and Kelly A. Ockunzzi and Virendra Singh and Kushal Kamal},
  year = {2019},
  doi = {10.1109/VLSID.2019.00037},
  url = {https://doi.org/10.1109/VLSID.2019.00037},
  researchr = {https://researchr.org/publication/ShenoyOSK19},
  cites = {0},
  citedby = {0},
  pages = {106-111},
  booktitle = {32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-0409-6},
}