A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS - researchr publication authors

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Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. In Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014. pages 1-2, IEEE, 2014. [doi]

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