Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura. A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. In Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014. pages 1-2, IEEE, 2014. [doi]
@inproceedings{ShibasakiCCDHTM14,
title = {A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS},
author = {Takayuki Shibasaki and Win Chaivipas and Yanfei Chen and Yoshiyasu Doi and Takayuki Hamada and Hideki Takauchi and Toshihiko Mori and Yoichi Koyanagi and Hirotaka Tamura},
year = {2014},
doi = {10.1109/VLSIC.2014.6858400},
url = {http://dx.doi.org/10.1109/VLSIC.2014.6858400},
researchr = {https://researchr.org/publication/ShibasakiCCDHTM14},
cites = {0},
citedby = {0},
pages = {1-2},
booktitle = {Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014},
publisher = {IEEE},
isbn = {978-1-4799-3327-3},
}