Power-Aware Compiler Controllable Chip Multiprocessor

Hiroaki Shikano, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara. Power-Aware Compiler Controllable Chip Multiprocessor. In 16th International Conference on Parallel Architecture and Compilation Techniques (PACT 2007), Brasov, Romania, September 15-19, 2007. pages 427, IEEE Computer Society, 2007. [doi]

Authors

Hiroaki Shikano

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Jun Shirako

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Yasutaka Wada

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Keiji Kimura

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Hironori Kasahara

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