An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs - researchr publication authors

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Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa. An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Transactions, 89-C(11):1535-1543, 2006. [doi]

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