Kenji Shimazaki, Makoto Nagata, Mitsuya Fukazawa, Shingo Miyahara, Masaaki Hirata, Kazuhiro Satoh, Hiroyuki Tsujikawa. An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. IEICE Transactions, 89-C(11):1535-1543, 2006. [doi]
@article{ShimazakiNFMHST06,
title = {An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs},
author = {Kenji Shimazaki and Makoto Nagata and Mitsuya Fukazawa and Shingo Miyahara and Masaaki Hirata and Kazuhiro Satoh and Hiroyuki Tsujikawa},
year = {2006},
doi = {10.1093/ietele/e89-c.11.1535},
url = {http://dx.doi.org/10.1093/ietele/e89-c.11.1535},
researchr = {https://researchr.org/publication/ShimazakiNFMHST06},
cites = {0},
citedby = {0},
journal = {IEICE Transactions},
volume = {89-C},
number = {11},
pages = {1535-1543},
}