Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita. Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA. pages 176-181, IEEE Computer Society, 2002. [doi]
@inproceedings{ShimizuIK02,
title = {Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits},
author = {Kazuya Shimizu and Noriyoshi Itazaki and Kozo Kinoshita},
year = {2002},
url = {http://csdl.computer.org/comp/proceedings/ats/2002/1825/00/18250176abs.htm},
researchr = {https://researchr.org/publication/ShimizuIK02},
cites = {0},
citedby = {0},
pages = {176-181},
booktitle = {11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA},
publisher = {IEEE Computer Society},
isbn = {0-7695-1825-7},
}