Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita. Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. In 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA. pages 176-181, IEEE Computer Society, 2002. [doi]
Abstract is missing.